EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations

Paper recorded by Signals 4 on 2026-09-22 in cs.LG. Abstract reproduced from arXiv; link to the original below.

Published 2026-09-22 on arXiv · recorded by Signals 4 on 2026-09-23

Category: cs.LG · 机器学习 · first seen 2026-09-23

Abstract

Large language models are increasingly used to generate SystemVerilog Assertions from natural-language specifica- tions and register-transfer-level designs. Existing datasets and benchmarks support important goals such as large- scale training, formal evaluation, specification-to-assertion generation, and mutation-based testing. A complemen- tary need is to study whether a generated assertion cap-

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